Among all metals in the world, three kinds of metal have lower resistivity than Al with a resistivity of 2.65 -cm: Gold (Au; 2.214 cm), copper (Cu; 1.678 cm), and silver (Ag: 1.587 cm). This will enable fabs to determine, during a pilot-line phase, where, when, and how often cleans should take place and what contamination level is acceptable. Hence, the area of IC chip can be approximately reduced by 50%, resulting in doubling of the IC chips produced in a fixed area. Currently, the first two steps are performed by sputtering and the last step uses Cu electroplating (ECP) method. In order to minimize the Blech effect on EM results, the length of the tested Cu line must be sufficiently long. ETH, Zurich. The indiffusion of copper and/or oxidation were performed in a rapid thermal annealing system. This results in a lower via resistance and a better reliability for Cu interconnects. In the last two steps, the selectivity should be considered because it is of importance to reach high-degreed planarization. In current Cu metallization, electroplating method is used to fill the high aspect ratio via and trench in the dual damascene structure. Generally, in the region of high Cu pattern density, the polishing rate is high and the thinning of the Cu line is observed due to a high polishing rate, resulting in a large variation in the resistance of the metal line. A sample of the pure element has never been assembled, because any macroscopic . Many wafer fabs do not possess a complete set of tools dedicated exclusively to copper-based, full-flow device processing, Thus, critical sophisticated tools such as those for metrology and lithography must accept copper-processed wafers and ensure that no contamination is transferred to non-copper wafers. The present invention defines a system (100) for detecting copper contamination within a semiconductor manufacturing process. In Cu lines with the smaller grain size, grain boundary diffusion can be significant during an EM stress, resulting in a lower EM lifetime [87]. TXRF data show that bare silicon wafers exposed to Cu contamination may still have extreme amounts of Cu after the cleaning process (see table). Whereas EM is induced by electron wind force under an electric field, stress-induced voiding (SIV) is due to stress migration. 1). The EM-induced void will form inside the via (early failure) and in the wire (late failure). The most common reduction products of nitric acid are NO2 (N = 4), NO (N = 2), and NH4+ (N = -3). J-C. Lin, C. Lee, A Study on the Grain Boundary Diffusion of Copper in Tantalum Nitride Thin Films, ECS and Solid-State Letters, pp. Actually, the EM lifetime decreases as shown in Figure7. The latter two materials (carbon nanotube and collective excitations) can provide a different conductance mechanism, but they are still in the research and development phase. - Conception and design of experimental setups and laser machine tools (kinematics and control). While working in the 1980s for a major semiconductor manufacturer, we had a major yield problem that was baffling the production team. CMP processes can only remove copper from the face of the wafer, leaving any film or contamination on the beveled edge free to migrate during subsequent operations. The biggest challenge for Cu sputtering process is to achieve good step coverage in the high aspect ratio via and trench. 5. The top Ti layer can provide good wetting of Cu film because Cu wetting on TiN is very poor. For the etching stop layer, also called Cu barrier dielectric layer, SiN or SiCN can be used, providing functions to protect Cu from oxidation and protect Cu from diffusion into the low-k dielectric during processing or device operation. Analytical cookies are used to understand how visitors interact with the website. Processes and procedures must be developed to control such cross-contamination without impacting cycle time, yield, and cost. The formed MnOx layer can act as a Cu barrier layer, thus avoiding depositing a metal barrier layer [47, 48]. Multichip Package According to the present invention, a semiconductor wafer (102) is transferred (108) from a semiconductor manufacturing component (104), which may have exposed the wafer to copper contamination, to a measurement system (106). The direct strategy to reduce the resistance rise is to decrease the thickness of the metal barrier film. The resistance is monitored as a function of time at the stress temperature [121]. So, a TaN/Ru or Ti/Ru bilayer is used for Cu diffusion barrier [54, 55, 56]. The cookie is set by GDPR cookie consent to record the user consent for the cookies in the category "Functional". Current Cu deposition methodologies do not ensure that the Cu film will only be deposited in the device region of the wafer. However, as the technology node is advanced to 0.25m, the back-end-of-line (BEOL) interconnect of ICs becomes the bottleneck in the improvement of IC performance [2]. CRC Handbook of Metal Etchants, eds. The obtained dielectric constant depends on the porosity. The built-up stress in the metal line is caused by two mechanisms: One is thermal stress due to thermal expansion mismatch between the metal line and the dielectric insulator; and the other is growth stress due to grain growth in the metal line [116, 117, 118]. Semiconductor Advanced Electronics Specialty Industrial Industrial Technologies Life & Health Sciences Research & Defense Support Global Service Field Service Extended Warranty Program Repair, Calibration & Refurbishment RMA Request Form Health & Safety Forms Contact Global Service Technical Support Product Technical Support Training Programs Furthermore, new technologies, such as electroplating and Cu CMP, have been used in the semiconductor fabrication line. View Semiconductor Products Semiconductor Applications View All Semiconductor Products Chemicals CMP Lithography Process gas filtration Process gas purification The team ran many experiments and tried several approaches to determine the source of the contamination. Adjusting the HF concentration enables rapid removal of oxide or nitride while the Cu contamination is being reduced. The chemical clean to remove Cu oxides can also minimize the detrimental effects caused by the Ar sputtering clean. Wafers partially contaminated by copper can be a source of contamination under some circumstances. In this step, removal selectivity is not considered because only Cu film is polished. Our team is growing all the time, so were always on the lookout for smart people who want to help us reshape the world of scientific publishing. Nickel alloys with: b.1.a. If silicon is left exposed not covered by tantalum tantalum-nitride, silicon oxide, or another barrier film Cu readily diffuses into it. Experiment and model results of electromigration lifetime scaling with the reduction of interconnect dimension. 139, p. 3317, 1992. The method includes the steps of providing the first layer having a partially . While a wafer backside and back edge can be hermetically sealed and protected from copper contamination during electroplating, the front-side exclusion zone and beveled edge are still vulnerable because clamping during electroplating is not a totally effective mask. Spinetch is a registered trademark of Merck Corp. Patrick S. Lysaght received his BSEE from the University of New Mexico and has 16 years of research experience at Los Alamos National Laboratory. Ru-based layer can provide a lower resistivity and a better Cu wettability than Ta layer; however, its Cu diffusion barrier is very poor. It is important to recognize that the duplication of sophisticated metrology and lithography tools can significantly impact cost-of-ownership in the manufacturing operation. The authors appreciate the exceptional support of Sematech, ERSO Taiwan, and SEZ's research labs in Austria and the US. 3. This would enable the semiconductor fab to determine the frequency of cleaning requirement and acceptability of the level of contamination. This produces the positive Cu ions, which in turn inject into the dielectric under the field along a fast diffusion path. Less stringent separation policies can be applied to operations such as finished goods, cleanroom supplies, wipedown areas, chemical and janitorial material transfers, or areas neutral to either process. Relative diffusivity of copper compared to other metals, at 700C, is shown in Figure 1. 181-183, April 1999. Melting point and resistivity of different metals. APPLICATIONS: Technical microscopy Flat-panel display inspection Semiconductor inspection & processing Widefield . Advanced; SDS; Certificates; Chemical Structure . This cookie is set by GDPR Cookie Consent plugin. CMP waste water treatment for semiconductor production During planarization of the wafer surfaces, waste water is generated that contains grinding aids and mostly copper ions from the removed copper coatings. London, SW7 2QJ, (A) Downstream stressing structure and (B) upstream stressing structure. On the other hand, the failure rate for stress-induced void in Cu line increases with increasing line width (Figure10) opposite to what is observed with Al line [116, 117, 122]. Cu film, barrier layer, and the dielectric are polished simultaneously. Removing Cu after an anneal is more difficult, but not impossible. All Rights Reserved. It had taken three months for the gold to diffuse from the outside to the inside of the tubes; it then began to ruin the wafers inside the tubes. Copper: Cu ~500, . This ratio increases further at lower temperature since at lower temperature the diffusivity of copper in silicon is even higher compared to other metals. For linear transistors, however, the gold just ruins the properties with excessive leakage and poor low-current amplification. However, the accompanied problems are poor step coverage and Cu diffusion into the dielectric. The resulting integration and reliability challenges are addressed as well. A successful plan will greatly minimize the risk of misprocessing or mishandling copper contaminated spare parts and greatly reduce the likelihood of this occurring. These should include appropriate protocols to prevent contamination between copper and non-copper via gowning, tool, workplace, and material segregation; a protocol for shared tools; development of fail-safe systems; and feasibility of decontamination of contaminated parts. 2 is predominant when Cu reacts with a mixture of equal volumes of concentrated nitric acid and water: 3Cu(s) + 8H+(aq) + 2NO3(aq)> (5) 3Cu2+(aq) + 4H2O(l) + 2NO(g). Void growth rate of stress-induced void as a function of temperature [116]. Hydrogen (H) atom is typically the reducing agent. The other stage is the completion of Cu CMP before a dielectric barrier layer deposition. Register to post a comment. Identification of materials. Additionally, in order to strengthen adhesion, a SiH4 exposure process is inserted between a plasma clean and a dielectric deposition processes to form a thin Cu silicide layer. This extra process to deposit a metal layer is very challenging because of selectivity deposition on the Cu lines. To satisfy the increasing demand for faster signal transport by the computing and telecommunication industries, copper thin film and low capacitance materials are becoming vital for high performance circuits of the future. The unique characteristic of stress-induced void is that the maximum rate of void growth in Cu line does not occur at a high temperature, as shown in Figure9. Semiconductor contamination: Not your usual suspects, DC/DC converter enables transition to 48-V infrastructure, Mid-range FPGAs decrease power, increase throughput, Omnivision shrinks image sensor for AR/VR/MR, Aggregation router boasts 2.4-Tbps switching, Cisco Linksys DPC3008: A DOCSIS 3 cable modem that worked great. As the dimensions of Cu interconnects shrink, these two processes are becoming more challenging. H. Oppolzer, W. Eckers, and H. Schaber, J. Phys. A number of surface (front and back) contamination and bulk recombination lifetime measurement tools or techniques can be used to monitor copper contamination on test wafers from a specific wafer processing tool. This leads to a larger RC delay in the advanced technology nodes, which surpasses the gate delay and becomes a limiting factor in ICs performance [3, 4, 5, 6]. Analysis of copper levels in the garments can be made by ICP/MS, followed by leaching with a solvent, to obtain a base line for non-contaminated gowns. Introduction. This is particularly true for non-DRAM fabs. One stage is via-opening before Cu metallization deposition. The earth-abundant semiconductor Cu 3 BiS 3 (CBS) exhibits promising photovoltaic properties and is often considered analogous to the solar absorbers copper indium gallium diselenide (CIGS) and copper zinc tin sulfide (CZTS) despite few device reports. Its based on principles of collaboration, unobstructed discovery, and, most importantly, scientific progression. The mechanism to remove Cu oxides in clean process can be achieved by either physical removal or chemical reaction [58]. How? These cookies ensure basic functionalities and security features of the website, anonymously. (To combat this concern, Sematech used to have copper Fridays Cu wafers were processed through lithography and other steps only on Fridays. Ionic contamination is a big concern in semiconductor manufacturing processes and in finished devices because small amounts of contamination (parts-per-billion (ppb) to parts-per-million (ppm) concentrations) can cause corrosion, erosion, electromigration, and shorting in devices, on wafers or in final individual electronic components. Emergency response plans need to be developed in case of copper contamination of tools and should be a part of operating procedures. Yields were decreasing on a daily basis because of high leakage failures. ECP process is performed by immersing the wafers in a solution containing cupric ions, sulfuric acid, and trace organic additives [36]. A dielectric film with the relative dielectric constant (k) lower than 4.0 (called low-k) had replaced a conventional chemical vapor deposition (CVD)-SiO2 film with a k value of 4.0 as an interconnect insulator because it can provide lower capacitance between the neighboring metal lines. . In such a case, Cu grain size would be much larger because Cu deposition is not restricted in the narrow lines. A thin layer of copper film was deposited on the back surface of the wafer. These apparent contradictions may result from the wide variety of plasma chambers and the plasma conditions. Expectations among semiconductor manufacturers that all wafers exiting a Cu process will meet specified contamination limits raises several issues: One strategy for isolation is to designate individual bays or tools as only for copper use and allowing particular types of carriers designated for copper use only. The integration of copper into semiconductor processing presents new opportunities and challenges. During the fabrication of Cu dual damascene structure, there are two stages in which Cu film could be exposed to air. Selecting this option will search all publications across the Scitation platform, Selecting this option will search all publications for the Publisher/Society in context, The Journal of the Acoustical Society of America, Impact of copper contamination on the quality of silicon oxides, Siemens AG, Components Division, Semiconductor Technology, OttoHahnRing 6, 8000 Munich 83, Federal Republic of Germany, Siemens AG, Corporate Research Laboratories, OttoHahnRing 6, 8000 Munich 83, Federal Republic of Germany. Carefully designed and operated cleanroom support can greatly reduced the risk of copper contamination. This is attributed to the enhanced adhesion between Cu line and barrier dielectric layer. Materials exposed to copper must be identified to prevent accidental mix-up with non-copper parts. The interfacial diffusion is considered to be the dominant Cu diffusion path. In order to mitigate and continue providing value to our customers, Cirtek has developed copper wire bonding technology since 2008. Hence, the energy and time in the Ar sputtering clean process must be carefully controlled in order to alleviate these two phenomena. L, W, and T are the length, width, and thickness of metal line, respectively. In a typical fab manufacturing microchips, the temperature, humidity and particle contamination in the air are The cookies is used to store the user consent for the cookies in the category "Necessary". FEOL process tools used in manufacturing, when gates are exposed, are considered to be high-risk tools. This chapter is organized as follows: in Section 2, we describe the process flow of Cu damascene metallization. Therefore, to mitigate Cu EM phenomenon, these related processes are needed to be optimized. Semiconductor Providing filtration, purification and separations solutions for a broad range of fluids, such as chemicals, gas, water, CMP slurries and photoresist. Aluminium Skived Heat Sinks Skived heat sinks are manufactured by peeling fins from a bar of solid copper or aluminum, using a sharp and Beliebt bei Jose Fonseca New Report Identifies Challenges to Continued U.S. Replacing these tubes upset the production-team members, but they felt that they had at least cured the contamination problem. Finally, low-k materials have lower thermal conductivity than does SiO2. Two mechanisms can explain this unique behavior. In this article, we discuss measures for minimizing and/or eliminating the copper contamination from the work and processes associated with the cleanroom environment. In the interview, Chandrasekaran pointed out that the company has set up Tata Electronics, "under which we are going to set up a semiconductor assembly testing business.". 1 Ohmi,T. Control of etchant viscosity, simultaneous radial and tangential etchant flows, and Bernoulli gas flow enables etching of Cu contamination from a wafer backside, and a wraparound effect that removes thin-film contamination from the beveled edge and front-side exclusion zone (0.5-5.0mm). These fabs need to integrate automation systems with contamination control strategies. Programs need to be developed to manage the supplier-supplied spare parts which might have been exposed to copper. This induces the loss of the insulating properties for a dielectric material for which the resistance state is converted from high to low. Failure rate of stress-induced void versus M2 line width and V2 via size after annealing stress at 225C for 1000h. Reproduced with permission from Ref. Finally, short conclusion and future trend for conductors used in the BEOL interconnects are provided in Section 6. Decontamination of copper parts should be carried out separately from the copper parts. This failure mode of stress-induced voids can be eliminated with good metal barrier layer coverage on the bottom and sidewalls of trenches and vias and void-free Cu-filling process. Stress-induced void in Cu lines are mostly observed under vias [116]. By clicking Accept All, you consent to the use of ALL the cookies. Proper protocols need to be developed to recover copper wafers which might have been broken accidentally in the process tools. Finally, a Ta layer is deposited. It is rare for one of the reactions to occur to the total exclusion of the other two. Comparison of various Cu deposition technologies. 4. (1) and (2), respectively. First, the modulus of the low-k dielectrics is lower than that of SiO2 film and decreases with the reduction of the dielectric constant. In the manufacturing of semiconductor devices copper lines and copper vias are used more and more instead of aluminium, although the metal contamination risk is much higher, the wall adhesion on dielectrics is worse, and the corrosion resistance of Cu is poor. This option allows users to search by Publication, Volume and Page. During chemical plasma clean process, Cu oxides can be reduced; however, the dielectric (e.g. These problems can be solved through: (i) reducing the down-force during Cu CMP process; (ii) improving the adhesion between layers in the interconnect; (iii) optimizing the used slurry; (iv) depositing a relatively dense material, such as SiO2 or nonporous SiCOH films on the top of the porous low-k dielectric film; and (v) performing an optimized wetting clean after the CMP process [70, 71, 72]. Such isolation might be total separation or partial area separation. 1 is predominant when concentrated (70%) nitric acid reacts with Cu [3]: Cu(s) + 4H+(aq) + 2NO3(aq)> (4) Cu2+(aq) + 2H2O(l) + 2NO2(g). Chlorine contamination, whether as chlorine or hydrogen chloride, are a most dangerous contaminant for metals. The first step is Cu film removal, stopping on the barrier layer. Table3 lists the properties of Cu films obtained by different deposition technologies. The improvement in EM lifetime is attributed to the effect of damage healing. The so-called chain effect from a single contaminated tool to many other tools can be prevented only by proper development of an appropriate segregation strategy. A carefully developed segregation strategy is key to the success of a contamination prevention program. Surface contamination measurement techniques include total reflection X-ray fluorescence spectroscopy (TXRF) and vapor phase decomposition followed by inductively coupled plasma-mass spectroscopy (VPD/ICP/MS). (Compare data in Fig. One is that the hydrostatic stress increases with increasing the width of Cu lines based on the result of stress simulation [123]. Side view schematic of electromigration test structures and void formation locations. Find the IoT board youve been searching for using this interactive solution space to help you visualize the product selection Cu diffusion into the dielectric leads to serious degradation in BEOL dielectrics reliability [157, 158, 159]. Therefore, the approaches to optimize Cu interfaces applied for EM improvement also provide great help for stress-induced void [129, 130, 131]. Hence, to remove Cu oxides and avoid Cu re-oxidation, an in situ clean is required. To minimize the damage on the porous low-k material, low-k material optimization and resist strip condition are chosen, and the process integration modification has been provided. The low-k materials currently used in the BEOL interconnects are SiOF (k=3.53.8), SiCOH (k=2.23.2), or air gap (k~1.0) [7, 8, 9, 10, 11]. Influence of copper contamination on recombination activity of misfit dislocations in SiGe/Si epilayers: Temperature dependence of activity as a marker characterizing the contamination level: Journal of Applied Physics: Vol 78, No 7 No Access Submitted: 23 January 1995 Accepted: 19 June 1995 Published Online: 17 August 1998 If the stress is high enough and the dielectrics are weak, metal extrusions may form, causing leakage between the neighboring metal lines [18, 75]. To solve this issue, new material such as tungsten (W), silicides, carbon nanotube, or collective excitations could be an alternative to Cu as interconnects [42, 43]. Additionally, the use of metal capping layers [133] and/or Cu alloying lines [106, 107], which are used to improve EM has also shown to reduce the failure rate of stress-induced void. Elevated levels of chloride (halogen) contamination can also serve to effectively mask any evidence of sulfur contamination on the corresponding copper coupons and can cause a large "unknown" copper corrosion film to appear. This loss of reliability is called time-dependent-dielectric breakdown (TDDB) [137, 138, 139, 140, 141]. There has also been tremendous progress in the manufacturing of ICs over the past 60years. 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